Generally, a supplementary redundancy cell is arranged on a memory cell periphery of a semiconductor device to prepare for the failure of a corresponding memory cell. The redundancy cell is connected to the memory cell via a fuse layer in the vicinity of the memory cell.
For instance, a fuse layer of a semiconductor device according to a related art is disclosed in detail in U.S. Pat. No. 5,759,877 for ‘Semiconductor fuse structure’, U.S. Pat. No. 5,963,825 for ‘Method of fabrication of semiconductor fuse with polysilicon plate’, ‘Semiconductor memory device with identification fuse’, or the like.
Generally, in case of the failure of a specific memory cell, the fuse layer connected to the specific memory cell is cut to isolate the specific memory cell from a circuit block. If the fuse layer is embedded within a structure of the semiconductor device, there exists a problem that the corresponding structure interrupts the process of cutting the fuse layer. In the related art, to solve the problem, a fuse layer is formed on a top layer of a semiconductor substrate to be exposed to an atmosphere. Hence, the fuse layer cutting process is facilitated without any obstacle.
In doing so, because the fuse layer is generally formed of metal and because the fuse layer is open to air, corrosion of the metal is inevitable. Considering the corrosion problem, a sort of an insulating layer is left on a fuse layer in fabricating a semiconductor device to play a role as a buffer layer. Hence, the unexpected corrosion of the fuse layer can be prevented.
As proposed in Korean Patent Application No. 1998-6141 for ‘Pad and fuse open process’ or Korean Patent Application No. 2000-26808 for ‘Method of forming fuse in semiconductor device’, the related art fuse layer is etched/formed together with a pad layer.
In case of etching/fabricating both pad and fuse layers, a step of removing an anti-reflective coating layer, e.g., a TiN layer, is provided to a top of the pad layer and a step of removing an insulating layer, e.g., an oxide layer, on the fuse layer are carried out by the same etch process. Yet, the anti-reflective coating layer provided to the top of the pad layer and the insulating layer on the fuse layer differ from each other in material. For instance, the anti-reflective coating layer has a relatively low etch rate and the insulating layer has an etch rate faster than that of the anti-reflective coating layer. Hence, even if the etch process for removing the anti-reflective coating layer and the insulating layer is collectively initiated at the same time, it is still difficult to simultaneously pattern them with a satisfactory result.
In case of carrying out a series of etch processes using the anti-reflective coating layer as the TiN layer as a target layer, it is advantageous that the anti-reflective coating layer provided to an outer side of the pad layer can be completely removed. Yet, in such a case, the insulating layer on the fuse layer is unnecessarily over-etched to bring about a problem that the fuse layer is exposed to the air.
On the contrary, in case of carrying out an etch process using the oxide layer as a target, the insulating layer remains on the fuse layer to prevent the corrosion of the fuse layer. Yet, in such a case, the anti-reflective coating layer of the pad layer fails to be fully removed to bring about a problem that a portion of the anti-reflective coating layer still remain on the outer side of the pad layer.
Hence, if the fuse layer is exposed to the air without a separate buffer layer, the exposed fuse layer reacts with oxygen in the air to accelerate its corrosion. Hence, the fuse layer is unable to play its normal role, whereby a quality of the semiconductor device is degraded.
On the other hand, if the anti-reflective coating layer remains on the outer side of the pad layer, adhesiveness with a wire bonded to the pad layer is abruptly lowered, the pad layer is discolored, and Galvanic corrosion occurs due to an electronegativity difference between a main metal layer, e.g., A1/Cu layer, of the pad layer and the anti-reflective coating layer. Hence, the quality of the semiconductor device is degraded as well.